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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity bp is
port(xh:in bit;
s1:in std_logic;
s2:in std_logic;
scut bit_vector(6 downto 0));
End bp;
Architecture bianping of bp is
Signal cnt:integer range 0 to 5;
Signal data: integer range 0 to 5;
begin
yi:process(xh,s1)
begin
if(s1'event and s1='0') then
if(cnt=5) then cnt<=0;
else cnt<=cnt+1;
end if;
end if;
end process;
er:process(cnt)
begin
case cnt is
when 1=>sc(1 downto 0)<=xh&'0';data<=1;
when 2=>sc(2 downto 0)<=xh&'0'&'0';data<=2;
when 3=>sc(3 downto 0)<=xh&'0'&'0'&'0';data<=3;
when 4=>sc(4 downto 0)<=xh&'0'&'0'&'0'&'0';data<=4;
when 0=>sc(6 downto 0)<=xh&'0'&'0'&'0'&'0'&'0'&'0';data<=0;
when others=>NULL;
end case;
end process;
san:process(s2,data)
begin
if(s2'event and s2='0') then
case data is
when 1=>sc(1 downto 0)<="00";
when 2=>sc(2 downto 0)<="000";
when 3=>sc(3 downto 0)<="0000";
when 4=>sc(4 downto 0)<="00000";
when 0=>sc(6 downto 0)<="0000000";
when others=>NULL;
end case;
end if;
end process;
end bianping;
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Errorine 9:File f:\bb\bp.vhd:Unsupported feature error:unresolved signal is multiply driven(µÚ¾ÅÐОé¼tÉ«µÄ)
Õˆ¸÷λ´ó‚bÖ¸üc£¬ÖxÖx£¡ ×÷Õß: asyou •rég: 2012-9-14 16:18
¿´¿´ÕZ·¨ÂÄãÒ»‚€Ý”³ößBÁ˶àÉÙ‚€Process°¡£¡ÄãÒªÓÃÖÐég׃Á¿Ìæ“Q£¬ÔÙ×ößx“ñ£¬»òÊÇÔÚÒ»‚€ProcessÀï×ößx“ñ£¡×÷Õß: ty1932 •rég: 2012-9-29 21:07
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