Cypress CY3280－22x45通用CapSense控制器開發方案
發布時間：2012-3-14 12:08
發布者：1770309616
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Cypress公司的CY3280-22x45汽車級PSoC 可編程片上系統,包含多個可配置的模擬和數字邏輯模塊，以及可編程互連。PSoC 采用功能強大的哈佛架構處理器,M8C處理器速度高達24MHz,8x8乘法器,32位累加器,可使用戶能夠根據每個應用的要求，來創建定制的外設配置,具有廣泛的應用。本文介紹了CY3280-22x45主要特性,方框圖以及通用CapSense控制器開發套件主要特性,電路圖,材料清單,PCB布局圖和元件分布圖. PSoC 可編程片上系統系列產品包含許多器件。 這些器件旨在使用一個低成本的單芯片可編程組件取代多個基于 MCU 的傳統系統組件。 PSoC 器件包含多個可配置的模擬和數字邏輯模塊，以及可編程互連。 這種架構使得用戶能夠根據每個應用的要求，來創建定制的外設配置。 此外，在一系列方便易用的引腳布局和封裝中還包含快速 CPU、閃速程序存儲器、SRAM 數據存儲器和可配置的 I/O。 CY3280-22x45主要特性: ■ Automotive Electronics Council (AEC) Q100 qualified ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 ℃ to +85 ℃ temperature range ❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 ℃ to +125 ℃ temperature range ■ Advanced peripherals (PSoC® blocks) ❐ Six analog Type ‘E’ PSoC blocks provide: • Up to four comparators with digital-to-analog converters (DAC) references • Up to 10-bit single or dual analog-to-digital converters (ADCs) ❐ Up to eight digital PSoC blocks provide: • 8 to 32-bit timers, counters, and pulse width modulators (PWMs) • One-shot, multi-shot mode in timers and PWMs • PWM with deadband in one digital block • Shift register, cyclical redundancy check (CRC), and pseudo random sequence (PRS) modules • Full- or half-duplex UARTs • SPI masters or slaves, 8- to 16-bit variable data length • Connectable to all general-purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ❐ Powerful synchronization support, analog module operations can be synchronized by digital blocks or external signals. ■ High-speed 10-bit successive approximation register (SAR) ADC with sample and hold optimized for embedded control ■ Precision, programmable clocking ❐ Internal oscillator up to 24 MHz ❐ High accuracy 24 MHz with optional 32-kHz crystal and phase locked loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low-power oscillator for watchdog and sleep functionality ■ Flexible on-chip memory ❐ Up to 16 KB flash program storage, 1000 erase/write cycles ❐ Up to 1 KB SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ■ Optimized CapSense® resource ❐ Supports two CapSense channels with simultaneous scanning ❐ Two current DACs provide programmable sensor tuning in firmware ❐ Two dedicated clock resources for CapSense Features ■ Automotive Electronics Council (AEC) Q100 qualified ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 ℃ to +85 ℃ temperature range ❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 ℃ to +125 ℃ temperature range ■ Advanced peripherals (PSoC® blocks) ❐ Six analog Type ‘E’ PSoC blocks provide: • Up to four comparators with digital-to-analog converters (DAC) references • Up to 10-bit single or dual analog-to-digital converters (ADCs) ❐ Up to eight digital PSoC blocks provide: • 8 to 32-bit timers, counters, and pulse width modulators (PWMs) • One-shot, multi-shot mode in timers and PWMs • PWM with deadband in one digital block • Shift register, cyclical redundancy check (CRC), and pseudo random sequence (PRS) modules • Full- or half-duplex UARTs • SPI masters or slaves, 8- to 16-bit variable data length • Connectable to all general-purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ❐ Powerful synchronization support, analog module operations can be synchronized by digital blocks or external signals. ■ High-speed 10-bit successive approximation register (SAR) ADC with sample and hold optimized for embedded control ■ Precision, programmable clocking ❐ Internal oscillator up to 24 MHz ❐ High accuracy 24 MHz with optional 32-kHz crystal and phase locked loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low-power oscillator for watchdog and sleep functionality ■ Flexible on-chip memory ❐ Up to 16 KB flash program storage, 1000 erase/write cycles ❐ Up to 1 KB SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ■ Optimized CapSense® resource ❐ Supports two CapSense channels with simultaneous scanning ❐ Two current DACs provide programmable sensor tuning in firmware ❐ Two dedicated clock resources for CapSense 
圖1.CY3280-22x45方框圖 CY3280-22x45通用CapSense控制器開發套件 This kit showcases the features of CY3280-22X45. The CY3280-22X45 family of PSoC® includes the following devices: CY8C21345-24SXI, CY8C22345-24SXI, and CY8C22545-24AXI. The 56-pin OCD part is assembled in the CY3280-22X45 Universal CapSense Controller Board. This part is used only for in-circuit debugging. The CapSense feature of CY8C22X45 can be implemented with the CY3280-SLM Universal CapSense Linear Slider Module. The two boards are connected by a 44-pin connector. The other features of CY3280-22X45 can be implemented with the CY3280-CPM1 Universal CapSense Plus Controller Module. The two boards are connected by a 40-pin connector. The CY3280-SLM Universal CapSense Linear Slider Module and the CY3280-CPM1 Universal CapSense Plus Controller Module can be connected with the CY3280-22X45 Universal CapSense Controller Board simultaneously.
圖2.CapSense控制器開發板外形圖 CY3280-22X45 Universal CapSense Controller Board CapSense控制器開發套件包括: ■CY3280-22X45 Universal CapSense Controller Board ■Printed Documents ■CY3280-22X45 Universal CapSense Controller Board CD ■CY3240-I2CUSB Board ■CY3210-MiniProg1 Programmer
圖3.CapSense控制器開發板電路圖 CapSense控制器開發板材料清單(BOM):
圖4.CapSense控制器開發板PCB布局圖
圖5.CapSense控制器開發板PCB頂層元件布局圖 詳情請見: 
CY8C21345_CY8C21645_CY8C22345_CY8C22645[1].pdf
(1.05 MB)
CY3280-22X45 Universal CapSense(R) Controller Development Kit Guide[1].pdf
(1.01 MB)
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